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audio/video switch with electronic volume for 3 scart description the CXA2125Q is an i 2 c programmable audio, video switch designed primarily for set top box applications. it interfaces from digital encoder sources to tv, vcr and auxiliary scart connectors. features 3 scart independent audio/video switching (tv, vcr, aux) 0 to ?3db volume control with click noise reduction 5 stereo audio inputs i 2 c control scart function switching input and output scart fast blanking for osd mono switchable to stereo on tv, vcr and aux outputs on-chip +12v to +9v voltage regulator logic output selectable +6db, +12db gain on tv output rgb input on vcr scart compatible with 2 scart audio/video switch cxa2126q applications digital set top box structure bipolar silicon monolithic ic absolute maximum ratings supply voltage v cc 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 850 mw operating conditions supply voltage 10.7 to 12 v operating voltage 9 0.5 v ?1 e99338b18 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA2125Q 64 pin qfp (plastic)
?2 CXA2125Q block diagram 2 2 rout2 31 lout2 32 mono switch 2 2 rout1 34 lout1 36 8db 1db 0/6db mono switch selectable gain stage mono switch vout7 100 ? 2 2 2 2 2 2 fblk_in1 dig typical connection vcr aux dig blue vcr blue aux blue dig green/cvbs vcr green aux green dig red/chroma dig chroma vcr red/chroma aux red/chroma dig cvbs/luma dig cvbs/luma vcr cvbs/luma aux cvbs/luma tv cvbs dig vcr aux tv analogue sat dig vcr aux tv analogue sat analogue sat cvbs tv_fblank +5v 0v fblk_in2 fblk_sw 100 ? fblk_in3 vin1 vin2 vin3 video_switch1 (tv) vin4 vin5 vin6 vin7 vin8 vin9 vin10 vin11 vin12 vin13 vin14 vin15 vin16 video_switch2 (vcr) video_switch3 (aux) audio_switch1 (tv) volume control & mute 8db zcd 1db 0/6db 52 53 51 63 61 13 2 59 15 4 6 57 17 8 10 55 21 23 25 vid_v cc vid_bias vid_gnd 60 62 7 bias bias 4.5v mute bias 1 4.05v aud_v cc dig_v cc aud_bias aud_gnd dig_gnd 20 19 26 bias 2 4.5v v cc _12v vreg_base vreg_9v 58 56 38 43 54 rin1 3 rin2 12 rin3 16 rin4 22 rin5 27 9v reg 6db 6db 6db 6db lin1 5 lin2 14 lin3 18 lin4 24 lin5 29 6db 6db hw_mute 45 sda 11 scl 9 fnc_vcr 64 fnc_aux 1 monitor monitor 6db 6db tv blue tv green tv red/c tv cvbs/y vcr chroma aux cvbs vcr cvbs/y typical connection 50 vout1 100 ? 48 2 vout2 100 ? 47 2 vout3 100 ? 46 2 vout4 100 ? 49 2 vout5 100 ? 41 2 vout6 100 ? 44 fnc_tv 30 logic 28 2 39 mono 33 phono_r 35 rtv 40 ltv tv 42 phono_l 37 audio_switch2 (vcr) audio_switch3 (aux) i 2 c interface logic p.o.d vcr aux tv vcr aux 3.3v or 5v
3 CXA2125Q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 fblk_in1 fblk_in2 vreg_9v vin13 vreg_base vin9 v cc _12v vin5 vid_v cc vin2 vid_bias vin1 fnc_vcr fnc_aux vin4 rin1 vin7 lin1 vin8 vid_gnd vin11 scl vin12 sda rin2 vin3 lin2 vin6 rin3 17 18 19 vin10 lin3 aud_bias fblk_in3 tv_fblank vout4 vout1 vout2 vout3 hw_mute vout6 dig_gnd ltv vout5 rtv vout7 dig_v cc phono_l lout1 33 34 35 phono_r rout1 mono lout2 rout2 fnc_tv lin5 logic rin5 aud_gnd vin16 lin4 vin15 rin4 vin14 aud_v cc pin configuration
4 CXA2125Q pin description pin no. symbol pin voltage equivalent circuit description 63 61 13 2 59 15 55 23 4 6 57 17 8 10 21 25 v cc = 12v v cc = 9v 14 a 120k ? 147 ? 60 a vin1 vin2 vin3 vin4 vin5 vin6 vin7 vin8 vin9 vin10 vin11 vin12 vin13 vin14 vin15 vin16 4.6v video signal inputs. an input coupling capacitor is required. (typ = 0.47f) 63 61 13 2 59 15 4 6 57 17 8 10 55 21 23 25 12 16 22 27 14 18 24 29 v cc = 12v 33k ? 33k ? 7 a 4.5v rin2 rin3 rin4 rin5 lin2 lin3 lin4 lin5 4.5v audio signal inputs. an input coupling capacitor is required. (typ = 2.2f) 12 16 22 27 14 18 24 29 48 47 46 49 41 44 39 v cc = 12v v cc = 9v 140 a 280 a 200 ? 100 ? vout1 vout2 vout3 vout4 vout5 vout6 vout7 3.9v video signal outputs. 48 47 46 49 41 44 39
5 CXA2125Q 35 37 33 40 34 31 42 36 32 v cc = 12v v cc = 9v 55 ? 20k ? 22k ? 20k ? 33 a 33 a rtv rout1 rout2 ltv lout1 lout2 phono_r phono_l mono 4.5v audio signal outputs. a coupling capacitor may be used. (typ = 10f) 40 34 31 42 36 32 35 37 33 pin no. symbol pin voltage equivalent circuit description 62 v cc = 12v v cc = 9v 14 a 11k ? 9k ? 200 ? bias_ video 3.9v reference bias for video circuit. connected to gnd with capacitor. (typ = 47f) 62 7 a 19 v cc = 12v v cc = 9v 20k ? 20k ? bias_ audio 4.5v reference bias for audio circuit. connected to gnd with capacitor. (typ = 22f) 19 30 v cc = 12v 120 ? 3k ? 15k ? fnc_tv i 2 c controlled output giving 0v, 6v or 12v. 30
6 CXA2125Q pin no. symbol pin voltage equivalent circuit description 120 a 54 v cc = 12v 77.7k ? 13.5k ? vreg_9v 9v pin connected to emitter of external regulator transistor. 54 56 v cc = 12v v cc = 12v 1ma 120 a 413 ? 15pf vreg_ base 9.7v connection to base of external regulator transistor. max i = 1ma 56 9 v cc = 9v 40 a 4k ? 10k ? 40k ? scl i 2 c clock input. 9 11 v cc = 9v 40 a 4k ? 4.5k ? 40k ? sda i 2 c data input/output. 11
7 CXA2125Q pin no. symbol pin voltage equivalent circuit description v cc = 12v 45 147 ? 28k ? 72k ? hw_mute hw mute: this pin is active high > 2.5v < 9v. when high, all audio muted. 45 28 v cc = 12v v cc = 9v 8 a 7.5k ? 3v 4.5k ? 40k ? logic open collector logic pins. 28 50 v cc = 12v v cc = 9v 100 a 100 a 100 ? 100 ? fblk_ out fast blank output set by i 2 c to input fblk_in1, fblk_in2, or fblk_in3. high = 5.3v low = 1.2v connected to external emitter follower. 50 52 53 51 v cc = 12v v cc = 9v 147 ? 90 a 50 a fblk_in1 fblk_in2 fblk_in3 fast blank inputs. low = < 0.4v high = > 1.0v, < 3.0v 52 53 51
8 CXA2125Q pin no. symbol pin voltage equivalent circuit description 80 a 64 1 12.5k ? 12.5k ? 10k ? 25k ? v cc = 9v fnc_vcr fnc_aux function switching input. (scart pin 8) 64 1 3 5 v cc = 12v 33k ? 7 a 4.5v rin1 lin1 4.5v audio signal inputs. a coupling capacitor is required for these inputs. (typ = 2.2f) 3 5
9 CXA2125Q electrical characteristics nominal conditions (ta = 25 c) v cc _12v = 12v, no signal, no load current consumption i cc 30 50 80 ma item symbol conditions min. typ. max. unit video system nominal conditions (ta = 25 c, vcc_12v = 12v, vreg_9v = 9v) input pin voltage output pin voltage with output on. output pin voltage with output off. gain bandwidth input dynamic range output dynamic range cross talk s/n ratio input impedance non-linearity differential gain differential phase sync crush v vpin v vpout1 v vpout2 gvv f v3db v drvi v drvo vctv s/n v zin v lin dg dp sc 4.3 3.6 5.5 15 2.5 5.0 94 3 3 3 2 4.6 3.9 0 6.0 20 72 120 0.4 1.5 1 0 4.9 4.2 0.2 6.5 50 175 3 2 2 2 v v v db mhz vp-p vp-p db db k ? % % deg % item symbol conditions min. typ. max. unit v2 v1 2 no signal, no load (fig.1) no signal, no load (fig.1) no signal, no load (fig.1) f = 200khz, 0.3vp-p input (fig.2) 0.3vp-p input, frequency where output level is 3db with 200khz serving as 0db (fig. 2) 200khz input (fig.2) 200khz, 2.5vp-p input (fig.2) f = 4.43mhz, 1vp-p input (fig.2) ratio of 0.7vp-p white video signal to "black line" noise. weighted using ccir 567. hpf @5khz, lpf @5mhz. (fig.2) 1vrms 1khz input through 56k ? . attenuation measured to calculate zin v (fig.3) (fig.4) v1 = pin voltage +0.5v, v2 = pin voltage +1v at output, non-linearity = 1 100 1.7vp-p 5-step modulated staircase. (chroma and burst are 150mvp-p 4.43mhz) (fig.2) as above. (fig.2) percentage reduction in sync pulse (0.4vp-p), with tip at 1.2v input offset. (fig.4) v2 v1 input pin v plus
10 CXA2125Q audio system unless otherwise stated: input coupling capacitor 1f; output coupling capacitor of 10f; load of 10k ? . nominal conditions (ta = 25 c, vcc_12v = 12v, vreg_9v = 9v) no signal, no load (fig. 5) f = 1khz, 0.5vrms input. tv output amplifier set to 0db (fig. 6) f = 1khz, 0.5vrms input. tv output amplifier set to +6db (fig. 6) f = 1khz, 1vrms input. (fig. 6) f = 1khz, 0.5vrms stereo input. tv output amplifier set to 0db (fig. 6) f = 1khz, 0.5vrms stereo input. tv output amplifier set to +6db (fig. 6) f = 1khz, 0.5vrms stereo input. (fig. 6) f = 1khz, 1vrms input. tv output amplifier set to 0db (fig. 6) f = 1khz, 1vrms input. tv output amplifier set to +6db (fig. 6) f = 1khz, 1vrms stereo input. tv output amplifier set to 0db (fig. 6) f = 1khz, 1vrms stereo input. tv output amplifier set to +6db (fig. 6) f = 1khz, 1vrms input. (fig. 6) f = 1khz, 1vrms stereo input. (fig. 6) 0.3vp-p input. output level at 30khz with 1khz serving as 0db. (fig. 7) 0.3vp-p input; frequency where output level is 3db with 1khz serving as 0db. no load (fig. 7) f = 1khz, 0.5vrms, unweighted response; lpf @400hz, hpf @80khz. (fig. 6) f = 1khz (fig. 6) f = 1khz (fig. 6) f = 1khz, 1vrms input on one input, measure on any other audio output. (fig.6) input/output pin voltage audio frequency response frequency b/w distortion input dynamic range rin2, 3, 4, 5 lin2, 3, 4, 5 input dynamic range rin1 lin1 cross talk (channel separation) v apin gv a1 gv a2 gv a3 gv a4 gv a5 gv a6 gv a7 gv a8 gv a9 gv a10 gv a11 gv a12 f af f bwa1 thd v da1 v da2 v cta 4.2 5.5 11 0.5 5.5 0.7 5 0.5 0.7 0.3 2 1 4.5 6 12 6 6 12 6 0 6 0 6 0 0 0 1 0.003 4.8 6.5 13 +0.5 6.5 +0.3 7 +0.5 +0.3 +0.3 0.2 76 v db db db db db db db db db db db db db mhz % vrms vrms db item symbol conditions min. typ. max. unit output tv/phono tv/phono vcr/aux tv mono tv mono vcr mono aux mono tv/phono tv/phono tv mono tv mono vcr/aux vcr mono aux mono gain input rin1/lin1 rin1/lin1 rin1/lin1 rin1 + lin1 rin1 + lin1 rin1 + lin1 rin2, 3, 4, 5 lin2, 3, 4, 5 rin2, 3, 4, 5 lin2, 3, 4, 5 rin2, 3, 4, 5 + lin2, 3, 4, 5 rin2, 3, 4, 5 + lin2, 3, 4, 5 rin2, 3, 4, 5 lin2, 3, 4, 5 rin2, 3, 4, 5 + lin2, 3, 4, 5
11 CXA2125Q offset voltage between input and output (fig. 5) (excluding any external series resistor) (excluding any external series resistor) (excluding any external series resistor) f = 1khz, 1vrms input to two channels. phase difference of stereo output measured f = 1khz, 1vrms input (at maximum volume). hpf @20hz, lpf@20khz. (fig. 6) f = 1khz, 0.5vrms input. set by i 2 c. (fig.6) f = 1khz, 0.5vrms input. set by i 2 c. (fig.6) f = 1khz, 1vrms input. (fig.6) offset voltage between any audio input and rtv, ltv outputs. (fig.5) dc offset input impedance rin2, 3, 4, 5 lin2, 3, 4, 5 input impedance rin1/lin1 output impedance phase difference s/n ratio electronic volume control fine volume attenuation step coarse volume attenuation step mute dc offset -rtv, ltv voff zin1 zin2 zout vpda s/n a a evc a evf amute vofftv 30 80 0.6 7.5 30 66 33 10 0.05 90 1 8 0 +30 1.4 8.5 80 +30 mv k ? k ? ? deg db db db db mv item symbol conditions min. typ. max. unit
12 CXA2125Q high level input voltage low level input voltage low level output voltage maximum clock frequency minimum waiting time for data change minimum waiting time for data transfer start low level clock pulse width high level clock pulse width minimum waiting time for start preparation minimum data hold time minimum data preparation time rise time fall time minimum waiting time for stop preparation i 2 c electrical characteristics nominal conditions (ta = 25 c, vcc_12v = 12v, vreg_9v = 9v) with sda, 3ma current supplied v ih v il v ol f scl t buf t hd;sta t low t high t su;sta t hd;dat t su;dat t r t f t su;sto 2.3 0 0 0 4.5 4.0 4.7 4.0 4.7 5 250 4.7 5.0 1.5 0.4 100 1 300 v v v khz s s s s s s ns s ns s item symbol conditions min. typ. max. unit
13 CXA2125Q 47 f bc547b +12v +9v 22 f sda scl +9v +9v +9v 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b measurement point measurement point v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 17 18 19 33 34 35 CXA2125Q v fig. 1. video system (d.c. test) d.c. measured from pins: 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 39, 41, 44, 46, 47, 48, 49, 55, 57, 59, 61, 63 notes) 1. all +9v supplies de-coupled close to supply pins, 20, 38, 60 with 10nf ceramic capacitor. 2. all video outputs are loaded with emitter follower during tests.
14 CXA2125Q 2.2 f input signal 47 f 75 ? 2.2 f 75 ? 2.2 f 75 ? 2.2 f bc547b +12v +9v 75 ? 2.2 f 75 ? 22 f 2.2 f 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 2.2 f 2.2 f 2.2 f 2.2 f 2.2 f sda scl +9v +9v +9v 2.2 f 2.2 f 1k ? +12v bc547b 2.2 f 75 ? 75 ? 75 ? 2.2 f 2.2 f 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b measurement point 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 17 18 19 33 34 35 CXA2125Q v signal applied to pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63 output signal measured from pins 39, 41, 44, 46, 47, 48, 49 notes) 1. all +9v supplies de-coupled close to supply pins, 20, 38, 60 with 10nf ceramic capacitor. 2. for tests requiring video measuring equipment with 75 ? input impedance, an external video line driver or buffer is used. 3. all video outputs are loaded with emitter follower during tests. fig. 2. video system (gain, dynamic range, bandwidth, differential gain, differential phase, crosstalk, signal to noise)
15 CXA2125Q 2.2 f 47 f 56k ? 2.2 f 56k ? 2.2 f 56k ? 2.2 f bc547b +12v +9v 56k ? 2.2 f 56k ? 22 f 2.2 f 56k ? 56k ? 56k ? 56k ? 56k ? 56k ? 56k ? 56k ? 2.2 f 2.2 f 2.2 f 2.2 f 2.2 f sda scl +9v +9v +9v 2.2 f 2.2 f 2.2 f 56k ? 56k ? 56k ? 2.2 f 2.2 f input signal 1khz measurement point v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 17 18 19 33 34 35 CXA2125Q fig. 3. video system (input impedance) signal applied and measured from pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63 notes) 1. all +9v supplies de-coupled close to supply pins, 20, 38, 60 with 10nf ceramic capacitor. 2. voltage measurements carried out with a high input impedance dvm. typically 10g ? .
16 CXA2125Q 47 f bc547b +12v +9v 22 f sda scl +9v +9v +9v 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b 1k ? +12v bc547b measurement point input signal psu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 17 18 19 33 34 35 CXA2125Q v fig. 4. video system (linearity) signal applied to pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63 output signal measured from pins 39, 41, 44, 46, 47, 48, 49 notes) 1. all +9v supplies de-coupled close to supply pins, 20, 38, 60 with 10nf ceramic capacitor. 2. all video outputs are loaded with emitter follower during tests.
17 CXA2125Q 47 f bc547b +12v +9v 22 f sda scl +9v +9v +9v input measurement point output measurement point v v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 17 18 19 33 34 35 CXA2125Q hw mute +5v 1k ? sw1 fig. 5. audio system (d.c. tests) d.c. measured from pins: 3, 5, 12, 14, 16, 18, 22, 24, 27, 29, 31, 32, 33, 34, 35, 36, 37, 40, 42 note) all +9v supplies de-coupled close to supply pins, 20, 38, 60 with 10nf ceramic capacitor.
18 CXA2125Q 47 f bc547b +12v +9v 22 f 2.2 f 600 ? 600 ? 600 ? 600 ? 600 ? 2.2 f 2.2 f sda scl +9v +9v 2.2 f 2.2 f 600 ? 2.2 f 600 ? 600 ? 2.2 f 2.2 f 600 ? 600 ? 2.2 f 2.2 f 10 f 10 f input signal measurement point v CXA2125Q 10k ? 10 f 10 f 10 f 10 f 10 f 10 f 10 f +9v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 17 18 19 33 34 35 hw mute +5v 1k ? sw1 signal applied to pins, 3, 5, 12, 14, 16, 18, 22, 24, 27, 29 output signal measured from pins 31, 32, 33, 34, 35, 36, 37, 40, 42 notes) 1. all +9v supplies de-coupled close to supply pins, 20, 38, 60 with 10nf ceramic capacitor. 2. when muting audio using hardware mute, sw1 is closed. fig. 6. audio system (gain, dynamic range, signal to noise, crosstalk, distortion, volume control)
19 CXA2125Q 47 f bc547b +12v +9v 22 f 2.2 f 600 ? 600 ? 600 ? 600 ? 600 ? 2.2 f 2.2 f sda scl +9v +9v 2.2 f 2.2 f 600 ? 2.2 f 600 ? 600 ? 2.2 f 2.2 f 600 ? 600 ? 2.2 f 2.2 f 10 f 10 f input signal measurement point v CXA2125Q 10 f 10 f 10 f 10 f 10 f 10 f 10 f +9v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 17 18 19 33 34 35 hw mute +5v 1k ? sw1 signal applied to pins, 3, 5, 12, 14, 16, 18, 22, 24, 27, 29 output signal measured from pins 31, 32, 33, 34, 35, 36, 37, 40, 42 notes) 1. all +9v supplies de-coupled close to supply pins, 20, 38, 60 with 10nf ceramic capacitor. 2. when muting audio using hardware mute, sw1 is closed. fig. 7. audio system (bandwidth)
20 CXA2125Q green digital encoder 2.2 f 2.2 f 1 f 1 f 10 f 10 f 560 ? 10 f 560 ? 1 f 1 f 47 f 10nf 10 f 75 ? 75 ? 1k ? 2.2 f +12v +12v +12v 2.2 f 2.2 f 2.2 f bc547b CXA2125Q bc547b bc547b bc547b 2.2 f 2.2 f 2.2 f 2.2 f 22 f 10 f 2.2 f 1 f 1 f 10k ? 10nf 10 f 10nf red chroma audio r audio l fast blank blue cvbs luma i 2 c 1 f tv scart vcr scart aux scart 1k ? 10k ? 75 ? 560 ? 10k ? 75 ? 19 17 21 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2 19 17 21 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2 19 17 21 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2 75 ? 1k ? 75 ? 75 ? 75 ? 10 f 560 ? 10 f 560 ? 10 f 560 ? 10 f bc547b +12v 75 ? bc547b 75 ? 1k ? rf modulator phono outputs lr bc547b 75 ? 1k ? bc547b 75 ? 1k ? bc547b +12v 75 ? 1k ? 1 f cvbs audio r audio l analogue satellite 75 ? 75 ? 75 ? 75 ? 75 ? 2.2 f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 fblk_in1 fblk_in2 vreg_9v vin13 vreg_base vin9 v cc _12v vin5 vid_v cc vin2 vid_bias vin1 fnc_vcr fnc_aux vin4 rin1 vin7 lin1 vin8 vid_gnd vin11 scl vin12 sda rin2 vin3 lin2 vin6 rin3 17 18 19 vin10 lin3 aud_bias fblk_in3 tv_fblank vout4 vout1 vout2 vout3 hw_mute vout6 dig_gnd ltv vout5 rtv vout7 dig_v cc phono_l lout1 33 34 35 phono_r rout1 mono lout2 rout2 fnc_tv lin5 logic rin5 aud_gnd vin16 lin4 vin15 rin4 vin14 aud_v cc application circuit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
21 CXA2125Q description of operation 1. explanation of video section the video section comprises of 16 high impedance inputs switched through to 7 video outputs. a +6db internal amplifier is connected to each output. the amplifier is required to compensate for the 6db attenuation which occurs at the external emitter follower stage used for driving video loads. all video outputs have an integrated 100 ? series protection resistor. the typical external configuration is shown in fig. 1-1. amp switch 1k ? 120k ? 75 ? 75 ? 0.47 f vbias vbias video element 75 ? 75 ? load +12v scart out scart in bc547b 100 ? vid_v cc = 9v fig. 1-1. video circuit element: 6db gain amplifier with external emitter follower switching the video outputs off each video output can be individually turned off using the i 2 c. when turned off, the output dc voltage is approximately 0v and hence the current consumption of the external emitter followers is reduced.
22 CXA2125Q 2. explanation of audio system inputs and outputs the audio system consists of 5 stereo inputs, 3 stereo outputs and separate mono and phono outputs. the stereo outputs can be connected to any one of the 5 stereo inputs. all audio inputs have a 6db attenuator except rin1 and lin1. thus, the net gain of the audio system is 0db, as the internal switch is followed by an audio amplifier having +6db of gain. the stereo input rin1/lin1 does not have an input attenuator and therefore the net gain from input to output is +6db. the output impedance of each audio amplifier is near zero, and can be capacitively coupled directly to the external scart circuit. the output circuitry is typically a 10f capacitor, and an optional 560 ? series compliance resistor. depending on the length and type of cable used in the scart cable connector, the load seen at the scart terminal will consist of a parallel capacitor, (100pf to 400pf) and mandatory 10k ? resistor connected to ground. the customer may chose to place an alternative audio filter at the av switch output. tv audio output the tv audio section is composed of an audio switch followed by two variable gain stages, corresponding to the coarse and fine electronic volume control. the coarse volume control gives a 0 to 56db range in 8db steps. similarly the fine control gives a 0 to 7db range in 1db steps. the volume control section is followed by a switchable 0/+6db amplifier which allows compensation for low level signals from a dac. finally, a mono switch allows the mixed r + l signal to be switched to the r and l output channels. (fig. 2-1) fig. 2-1. tv audio output tv mute the i 2 c mute function acts only on the tv, phono and mono audio circuit. audio mute can be implemented after a audio zero cross detection to reduce click noise, or immediately depending on the i 2 c setting of zcd. it can be seen from the i 2 c write format that the same mute bit occurs in data 1 and data 7. this allows the software to action an immediate mute, make any suitable changes to the audio source or electronic volume control and after a minimum period of 6 90s (540s) un-mute the output buffer. such a period provides ample time to allow any transient ac voltages to settle during an audio source change. 10 f 560 ? c scart pin optional low pass filter tv audio output volume control 8db 1db 0/6db mono switch 2 2 2 2 8db zcd 1db 0/6db rin1 1 f audio source 3 rin2 12 rin3 16 rin4 22 rin5 27 6db 6db 6db 6db lin1 5 lin2 14 lin3 18 lin4 24 lin5 29 6db 6db 6db 6db mute phono_r 35 rtv 40 ltv 42 phono_l 37
23 CXA2125Q zero cross detector (zcd) the zero cross detector reduces the effect of "click noise" when implementing a volume change or an audio mute. the change volume or mute instruction sent by i 2 c will only be implemented when a minimal (ie zero cross) signal amplitude is detected. the zero cross detection circuit can be turned off by setting the "zcd" bit low in the i 2 c write mode. hardware mute a hardware mute pin is provided which will mute all audio outputs when the pin voltage exceeds 2.5v. this muting is instantaneous. vcr and aux output the outputs rout1, 2 and lout1, 2 have a fixed gain of 0db from the input. if any attenuation is required then it is possible to insert a series resistance on the input. (fig. 2-2) 10 f 560 ? c scart pin optional low pass filter vcr and aux audio circuit mono switch 2 2 rin1 1 f audio source 3 rin2 12 rin3 16 rin4 22 rin5 27 6db 6db 6db 6db lin1 5 lin2 14 lin3 18 lin4 24 lin5 29 6db 6db 6db 6db mute rout1/2 34 31 36 32 lout1/2 fig. 2-2. vcr and aux audio output phono outputs there is a stereo phono output which carries the same signal as the tv output. this is typically used for connection to a hi-fi. the user may connect an external attenuator which is a.c. coupled to the outputs.
24 CXA2125Q i 2 c data interface table ic control data format slave address a data1 a data2 a data3 a data4 a datan a p s s: start condition a: acknowledge p: stop condition address = 90h i 2 c data structure (write mode) address data1 data2 data3 data4 data5 data6 data7 b7 1 evc vid_switch 1 tv vid_switch 2 vcr vid_switch 3 aux mono vcr mono tv mono aux fblk fnc logic tv aud gain vout5 mute not used not used not used not used not used not used not used not used not used not used not used tv aud mute b6 0 b5 0 b4 1 evf b3 0 b2 0 b1 0 b0 0 = write tv aud mute z.c.d aud_switch 1 tv aud_switch 2 vcr aud_switch 3 aux vout2 on/off vout3 on/off vout4 on/off vout1 on/off vout6 on/off vout7 on/off vout5 on/off key evc: electronic volume course (8db steps) evf: electronic volume fine (1db steps) tv aud mute: tv audio mute. controls the tv audio output buffer. (same bit appears in data 1 & 7) z.c.d: zero cross detector active. when zcd = 1 volume and mute change at zero cross. vid_switch 1: selects the input video sources for vout1, vout2, vout3, vout4 vid_switch 2: selects the input video sources for vout5, vout6 vid_switch 3: selects the input video sources for vout7 aud_switch 1: selects one of 5 stereo inputs for rtv, ltv, phono_l, phono_r, mono aud_switch 2: selects one of 5 stereo inputs for rout1, lout1 aud_switch 3: selects one of 5 stereo inputs for rout2, lout2 fnc: video function switch control fblk: video fast blanking control logic: logic outputs (open collector). 0 = high impedance. 1 = current sink mode.
25 CXA2125Q i 2 c data format (read mode) slave address a data8 p na s na: no acknowledge i 2 c data structure (read mode) address data b7 1 x b6 0 x b5 0 zc status b4 1 p.o.d. fnc_aux b3 0 b2 0 b1 0 b0 1 = read fnc_vcr key fnc_vcr: at pin 64, av switch monitors the voltage of pin 8 from vcr scart, and records status. fnc_aux: at pin 1, av switch monitors the voltage of pin 8 from aux scart, and records status. zc status: zc status = 1 indicates that zero cross condition has been achieved after the zcd is turned on. p.o.d.: power on detect. p.o.d. = 1 when dig_v cc voltage rises above a threshold level of approximately 5v.
26 CXA2125Q 3. video input i 2 c control switch 1 (tv output) data 2 bits 3, 4, 5 vout1 (b) switch setting vout2 (green) vout3 (r/c) vout4 (cvbs/y) comment vin1 bias vin2 vin3 bias bias bias bias 0xx000xxx 1xx001xxx 2xx010xxx 3xx011xxx 4xx100xxx 5xx101xxx 6xx110xxx 7xx111xxx vin4 bias vin5 vin6 bias bias bias bias vin7 vin8 vin9 vin10 vin7 bias bias bias vin11 vin12 vin13 vin14 vin4 vin15 vin16 bias digital encoder digital encoder vcr aux digital encoder tv analogue satellite video mute vout5 (chroma (c)) switch setting vout6 (cvbs/y) comment vin7 vin8 vin9 vin10 vin7 bias bias bias 0xx000xxx 1xx001xxx 2xx010xxx 3xx011xxx 4xx100xxx 5xx101xxx 6xx110xxx 7xx111xxx vin11 vin12 vin13 vin14 vin4 vin15 vin16 bias digital encoder digital encoder vcr aux digital encoder tv analogue satellite video mute note) after power on all tv outputs are off and muted. switch 2 (vcr output) data 3 bits 3, 4, 5 note) after power on vcr outputs are off and muted. vcr chroma mute data 3 bit 7 0 x x x x x x x = vout5 active. connected to input specified in above table. 1 x x x x x x x = vout5 muted (the output dc bias still remains).
27 CXA2125Q switch 3 (aux output) data 4 bits 3, 4, 5 vout7 (cvbs) switch setting comment vin11 bias vin13 vin14 vin4 vin15 vin16 bias 0xx000xxx 1xx001xxx 2xx010xxx 3xx011xxx 4xx100xxx 5xx101xxx 6xx110xxx 7xx111xxx digital encoder video mute vcr aux digital encoder tv analogue satellite video mute note) after power up the aux video outputs are off and muted. standby mode control data 6 bits 0, 1, 2, 3, 4, 5, 6 each video output can be individually turned off using data byte 6. 0 = video output off 1 = video output on note) when switched off, the video outputs are high impedance to prevent d.c. driving of the external emitter follower stage. the reduction of overall current consumption will depend on how many video outputs are turned off. after power on all video outputs are in the off state.
28 CXA2125Q 4. fast blanking operation (pin 16 on scart), fblk the fast blanking signal instructs the tv to select either the external cvbs information or the external rgb information. this is used to superimpose an on screen display (osd) presentation (normally rgb) upon a cvbs background. fast blanking information has the same nominal phase as the rgb and cvbs signal, and is defined as follows, fast blanking output at scart, 1. cvbs mode scart pin voltage = 0 to 0.4v 2. rgb mode scart pin voltage = 1 to 3.0v threshold voltage is approximately 0.75v at the scart input. fast blanking i 2 c control in the CXA2125Q, there are three fast blanking inputs, one associated with the digital encoder input (fblank_in1), one with the vcr rgb/cvbs input (fblank_in2), and another associated with the aux rgb/cvbs input (fblank_in3). these can be selected by i 2 c. in addition to the two blanking inputs, the fast blank pin output can be set to a constant 0v or 5v by means of the i 2 c control. hence there are four possible states. these are controlled according to the following table. fblk control data 5 bits 3, 4, 5 note) after power on the output is 0v. fast blank output circuit the output requires an external buffer stage to drive the required 75 ? scart termination. the levels at the ic output are 0v and +5v. fast blank output i 2 c setting 0v +5v same level as fast blank in 1 (0/+5v) same level as fast blank in 2 (0/+5v) same level as fast blank in 3 (0/+5v) +5v +5v +5v 0xx000xxx 1xx001xxx 2xx010xxx 3xx011xxx 4xx100xxx 5xx101xxx 6xx110xxx 7xx111xxx 1k ? 75 ? 75 ? scart line 16 v cc tv fast blank 0v/5v CXA2125Q fig. 4-1. fast blanking interface to tv scart
29 CXA2125Q 5. function switch, fnc. the function switch facility is designed to read the status of the scart function pin 8 from the vcr input. the read register holds the status of the input function lines. the function output is controlled by i 2 c and is used to change the voltage on the function line to the tv. the output can be connected directly to the scart pin. (fig. 5-1) read mode reads the status of the inputs fnc_vcr and fnc_aux. 0 0 1 b1/b3 0 1 1 b0/b2 0 to +2v (default) +4.5 to +7v +9.5 to +12v fnc_vcr/fnc_aux (internal tv) (16:9 external) (4:3 external) level (scart defn.) read data8 input pin voltage write mode controls the voltage at the tv function line (pin 8) mode/(typical pin voltage) i 2 c control (data 5) internal tv/(1v) external scart input 16:9 mode/(6v) external scart input 4:3 mode/(11v) external scart input 4:3 mode/(11v) 0 xxxxx00x 1 xxxxx01x 2 xxxxx10x 3 xxxxx11x note) after power on output is internal tv mode ie. 0v at the pin. 10k ? scart pin 8 < 2v > 4.5v < 7v > 10v fnc_tv CXA2125Q fig. 5-1. tv function switch output
30 CXA2125Q 6. logic output a single logical output pin is provided. this is controlled via the i 2 c and is an open collector output. specification i 2 c bit 0 = open collector/high output impedance i 2 c bit 1 = vsat (to 0.2v) vmax at logic pin = 12v imax during current sink = 1ma logic cct. i 2 c logic open collector logic outputs fig. 6-1. logic output interface
31 CXA2125Q 7. i 2 c audio signal control outputs tv, vcr, aux data 2, 3, 4 bits 0, 1, 2 rin1 rin2 rin3 rin4 rin5 audio mute audio mute audio mute lin1 lin2 lin3 lin4 lin5 audio mute audio mute audio mute rtv, rout1, rout2 ltv, lout1, lout2 0db 1db 1db 3db 4db 5db 6db 7db volume control fine data 1 bits 2, 3, 4 volume control coarse data 1 bits 5, 6, 7 switch setting 0 xxxxx000 1 xxxxx001 2 xxxxx010 3 xxxxx011 4 xxxxx100 5 xxxxx101 6 xxxxx110 7 xxxxx111 note) after power on the audio outputs are muted. setting volume fine control gain 0xxx000xx 1xxx001xx 2xxx010xx 3xxx011xx 4xxx100xx 5xxx101xx 6xxx110xx 7xxx111xx 0db 8db 16db 24db 32db 40db 48db 56db setting gain 0 000xxxxx 1 001xxxxx 2 010xxxxx 3 011xxxxx 4 100xxxxx 5 101xxxxx 6 110xxxxx 7 111xxxxx
32 CXA2125Q tv output amplifier data 7 bit 6 x0xxxxxx= 0db x 1 x x x x x x = +6db note) after power on the gain is set to 0db. tv mono switch data 7 bit 3 x x x x 0 x x x = normal stereo output x x x x 1 x x x = mono signal switched onto r + l line. vcr mono switch data 7 bit 4 x x x 0 x x x x = normal stereo output x x x 1 x x x x = mono signal switched onto r + l line. aux mono switch data 7 bit 5 x x x 0 x x x x = normal stereo output x x x 1 x x x x = mono signal switched onto r + l line. mute and zero cross operation for tv, phono and mono outputs. there are two mute control bits in the bus map to allow the tv outputs to be muted before the channel change instruction occurs. the normal structure for a click free audio channel change is as follows: data 1 mute the tv audio output with the zcd switched on. data 2 change the tv audio source. data 7 un-mute the tv audio output again with the zcd switched on. note) after power on tv mute and zcd are set to 0. tv aud mute data 1 bit 1 data 7 bit 7 zcd data 1 bit 0 rtv, ltv, phono_r, phono_l, mono outputs 0 0 1 1 0 1 0 1 un-mute immediately un-mute on next zero cross mute immediately mute on next zero cross
33 CXA2125Q notes on operation 1) supply de-coupling capacitors, 10nf and 4.7f in parallel should be inserted as close to the supply pins, 20, 38, 60 as possible. 2) to minimize crosstalk, attention should be given to the routing of audio and video to the ic inputs. pcb track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 3) attention should be given to the electrolytic capacitors on the input and output signal pins. as the pin's voltage is between 3.7v and 4.7v dc the positive terminal on the capacitor should be orientated towards the pin. 4) the audio outputs may be muted at any time after power up by connecting the hw_mute pin (45) to a voltage > 2.5v and < 9v. 5) when driving video loads with impedance = 75 ? an emitter follower or video line driver is required to be connected at the video outputs as shown in the application schematic. stray capacitance on pins vout1-8 must be kept to a minimum by placing loads as close to the pins as possible. 6) the supply voltage on pin 58 "v cc _12v" should not exceed +12v. if the supply has poor regulation then a series diode or zener diode may be used to limit the voltage at this pin.
34 CXA2125Q inputs rin1, lin1 selected input [vrms] 0 1 0.1 0.01 0.001 0.5 1 1.5 thd [%] audio frequency characteristics frequency [hz] input = 0.3vp-p 100 4 0 2 4 2 6 1k 10k 100k 1m 10m audio output/input gain [db] inputs rin2, 3, 4, 5/lin2, 3, 4, 5 selected input [vrms] 0 0.1 0.01 0.001 0.0001 1 2 3 3.3 thd [%] video frequency characteristics frequency [hz] 100k 4 6 8 0 2 1m 10m 50m video output/input gain [db] typical audio output distortion
35 CXA2125Q sony code eiaj code jedec code 23.9 0.4 20.0 ?0.1 0.4 ?0.1 + 0.15 14.0 ?0.1 1 19 20 32 33 51 52 64 0.15 ?0.05 + 0.1 2.75 ?0.15 16.3 0.1 ?0.05 + 0.2 0.8 0.2 m 0.2 0.15 + 0.4 17.9 0.4 + 0.4 + 0.35 64pin qfp (plastic) qfp-64p-l01 p-qfp64-14x20-1.0 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 1.5g 1.0 0 ? to10 ? sony corporation pec product sony code eiaj code jedec code 23.9 0.4 20.0 0.1 0.4 0.1 + 0.15 14.0 0.1 1 19 20 32 33 51 52 64 0.15 0.05 + 0.1 2.75 0.15 16.3 0.1 0.05 + 0.2 0.8 0.2 m 0.2 0.15 + 0.4 17.9 0.4 + 0.4 + 0.35 64pin qfp (plastic) qfp-64p-l01 p-qfp64-14x20-1.0 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 1.5g 1.0 0 ? to10 ? lead specifications item lead material 42 alloy solder plating sn-bi bi:1-4wt% lead treatment thickness 5-18 m spec.

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